Michal Siwinski

3131 Homestead Rd #6U
Santa Clara, CA 95051

(408)554-7133

E-mail: michal@alumni.EECS.Berkeley.edu

Home Page:http://alumni.eecs.Berkeley.edu/~michal


Objective:

To expand my knowledge of ASIC and microprocessor design, and implement
complex hardware projects. Design Consulting and start-up experiance.

Education:

University of California, Berkeley
B.S. in Electrical Engineering and Computer Science (EECS), May 1997

Work Experience:

ASIC Designer at Mentor Graphics, (Present)
Provide top-down expertise as well as ASIC front end design experience to numerous clients of Mentor Consulting. Provide close cooperation with system architecture, design verification, and test groups to produce customized products for customers which meet all of the customers which meet all of the companies performance levels. Ensure compatibility, reliability, scheduling, and manufacturability goals.

Teaching Assistant at University of California, Berkeley, (Spring '97)
Assisted with teaching graduate level VLSI Systems Design course.

Competitive Marketing Applications Engineer at Xilinx, (Summer 1996)
Conducted benchmarks and performance analysis for Altera and Xilinx Field Programmable Gate Array (FPGA) markets. Implemented various hardware designs, performed layout optimization and floor planning.

Projects:

Parallel Port front-end IP creation
Designed an IP Soft Core. Implemented design for various customers.

Microprocessor Re-Target
Re-Target to TSMC 0.5um library, including synthesis, verification, and clock tree insertion. Aproximate size ~600K gates.

Superscalar MIPS RISC processorbr> Included an instruction fetch stage feeding two four-stage pipelines. Designed most modules in VHDL including cache and memory controller.

XTEK Start-up Company
Performed as VP Engineering. Developed and presented a business plan for a high-tech company.

Technical skills:

Languages: Verilog, VHDL, C/C++, MIPS Assembly, LISP, Scheme, Pascal, Perl
CAD Tools: Mentor Tool Flow, ModelSim, Renoir, Quick HDL, QuickSim, Leonardo, Verilog-XL, Design Compiler, XACT, Foundation, MaxPlus II, Powerview, Viewlogic, Magic
others: gcc/g++, gdb, espresso, Word, Excel, Powerpoint, Framemaker

Special skills:

Leadership and organizational skill, Project Management experience
Fluency in Spanish and Polish

Papers:

Lead into Gold - Design Reuse Alchemy, IP'98 Conference, October 1998.

Interests:

skiing, soccer, tennis, photography, drawing, poetry, my friends, life!


This resume last updated on 8/19/98